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ADSP-21160 - DSP Microcomputer

General Description

The ADSP-21160 SHARC DSP is the first processor in a new family featuring Analog Devices’ Super Harvard Architecture.

Easing portability, the ADSP-21160 is application source code compatible with first generation ADSP-2106x SHARCs in SISD (Single Instruction, Single Data) mode.

Key Features

  • High performance 32-bit DSP.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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a Preliminary Technical Data SUMMARY • DSP Microcomputer ADSP-21160 KEY FEATURES • • • • • • • • • • • High performance 32-bit DSP—applications in audio, medical, military, graphics, imaging, and communication Super Harvard Architecture—four independent buses for dual data fetch, instruction fetch, and nonintrusive, zero-overhead I/O Backwards compatible—assembly source level compatible with code for ADSP-2106x DSPs Single-Instruction-Multiple-Data (SIMD) computational architecture—two 32-bit IEEE floating-point computation units, each with a multiplier, ALU, shifter, and register file Integrated peripherals—integrated I/O processor, 4 Mbit on-chip dual-ported SRAM, glueless multiprocessing features, and ports (serial, link, external bus, & JTAG) CO RE PROCESSO R TI MER I NST RU C TI